Faculty
Chenchang Zhan is an Associate Professor with the School of Microelectronics (National Exemplary School of Microelectronics), the Southern University of Science and Technology (SUSTech), Shenzhen, China. He received the B.Sc. degree in electrical engineering and the M.Sc. degree in microelectronics from Fudan University, Shanghai, China, in 2004 and 2007, respectively, and the Ph.D. degree in electronic and computer engineering from the Hong Kong University of Science and Technology (HKUST), Hong Kong SAR, China, in 2011. From 2006 to 2007, he was an Intern Analog Design Engineer with VeriSilicon, Shanghai, China. From 2011 to 2012, he worked as a post-doctoral Research Associate with HKUST. From 2012 to 2014, he was with Qualcomm Inc., San Diego, CA, as a Senior Engineer, focusing on the design of high-performance power converters for future generations of mobile devices. He then joined SUSTech as an Assistant Professor in Aug. 2014, and was promoted to an Associate Professor in Dec. 2019. His research interests include the analysis and design of analog, mixed-signal and power management integrated circuits and systems for a variety of applications. Up to date, he published 1 book, >90 SCI/EI/IEEE papers, and was granted with 11 China and 6 US patents. He received the Best Paper Award from IEEE ISIC'2009, Singapore and IEEE EDSSC'2018, Shenzhen, the Best Student Paper Award from IEEE EDSSC'2010, Hong Kong, the Best Student Paper Award from IEEE ISCAS'2011, Rio de Janeiro, Brazil, the 2018 SUSTech Young Faculty Research Award, the 2019 SUSTech Excellent Teacher of the Year Award, the 2019 SUSTech Excellent Residential College Mentor of the Year Award, the 2020, SUSTech 5-Year Service Award, and the 2022 IEEE ICTA Top 10 Paper Contributors in 5 Years Award. He served as a Review Committee Member for IEEE APCCAS'2014, an Organization Committee Member for IEEE APCCAS’2022, a Technical Program Committee member for IEEE ICTA'2018-2022, a Guest Editor for Hindawi APEC, a Session Chair/Co-Chair for IEEE ISCAS'2018-2019 and ICTA'2018-2022, as well as a reviewer for many reputational international journals and conferences. He is a Senior Member of IEEE.
Education
2007-2011, Ph.D. in electronic and computer engineering, Hong Kong University of Science and Technology
2004-2007, M.Sc. in microelectronics, Fudan University
2000-2004, B.Sc. in electrical engineering, Fudan University
Work Experiences
2020-present, Associate Professor, Southern University of Science and Technology
2014-2019, Assistant Professor, Southern University of Science and Technology
2012-2014, Senior Engineer, Qualcomm Inc., San Diego, CA
2011-2012, Postdoctoral Research Associate, Hong Kong University of Science and Technology
2006-2007, Intern Analog Design Engineer, VeriSilicon, Shanghai, China
Research Areas
Power management and energy harvesting integrated circuits and systems
Analog and mixed-signal integrated circuits
Low-power integrated circuit design methodology
ResearcherID Link: https://publons.com/researcher/1807217/chenchang-zhan/
Google Scholar Link: https://scholar.google.com/citations?user=tYZ863gAAAAJ&hl=en
Honors and Awards
2022, IEEE ICTA Top 10 Paper Contributors in 5 Years
2021, Excellent Advisor Award, National University IC Innovation & Entrepreneurship Competition
2020, Excellent Advisor Award, Huawei Ecology University ICT Competition
2020, SUSTech 5-Year Service Award
2019, Elevated to be IEEE Senior Member
2019, SUSTech Excellent Teacher of the Year Award
2019, SUSTech Excellent Residential College Mentor of the Year Award
2018, SUSTech Young Faculty Research Award
2018, Best Paper Award, IEEE EDSSC
2017, Excellent Advisor Award, SUSTech Innovation and Entrepreneurship Competition
2016, Excellent Advisor Award, National University IC Design Competition (NUICDC)
2016, SUSTech Excellent Individual for UG Admission Initiatives
2016, SUSTech Shuren Residential College Mentor of the Year Award
2016, Nanshan Leading Talent Tier C, Nanshan District, Shenzhen, Guangdong
2014, Peacock Talent Tier C, Shenzhen, Guangdong
2011, Best Student Paper Award, IEEE ISCAS
2010, Best Student Paper Award, IEEE EDSSC
2009, Best Paper Award, IEEE ISIC
2009, Best Paper Award Nomination, IEEE ISCAS
Selected Publications
1. J. Lin, Y. Lu, C. Zhan and R. P. Martins, "A single-stage dual-output regulating rectifier with hysteretic current-wave modulation," IEEE J. Solid-State Circ., vol. 56, no. 9, pp. 2770-2780, Sept. 2021.
2. J. Lin, C. Zhan and Y. Lu, "A 6.78-MHz single-stage wireless power receiver with ultra-fast transient response using hysteretic control and multilevel current-wave modulation," IEEE Trans. Power Elec., vol. 36, no. 9, pp. 9918-9926, Sept. 2021.
3. G. Cai, Y. Lu, C. Zhan and R. P. Martins, "A fully integrated FVF LDO with enhanced full-spectrum power supply rejection," IEEE Trans. Power Elec., vol. 36, no. 4, pp. 4326-4337, Apr. 2021.
4. Q. Huang, C. Zhan, and J. Burm, "A 4-MHz digitally controlled voltage-mode buck converter with embedded transient improvement using delay line control techniques," IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 67, no. 11, pp. 4029-4040, Nov. 2020.
5. L. Wang and C. Zhan, “A 0.7-V 28-nW CMOS subthreshold voltage and current reference in one simple circuit,” IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 66, no. 9, pp. 3457-3466, Sept. 2019.
6. Y. Tan, C. Zhan and G. Wang, "A fully-on-chip analog low-dropout regulator with negative charge pump for low-voltage applications," IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 66, no. 8, pp. 1361-1365, Aug. 2019.
7. C. Zhan, G. Cai and W. H. Ki, “A transient-enhanced output-capacitor-free low-dropout regulator with dynamic miller compensation,” IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 27, no. 1, pp. 243-247, Jan. 2019.
8. H. Li, C. Zhan and N. Zhang, "A fully-on-chip digitally assisted LDO regulator with improved regulation and transient responses," IEEE Tran. Circ. Syst. I: Reg. Papers, vol. 65, no. 11, pp. 4027-4034, Nov. 2018.
9. Q. Huang, C. Zhan, and J. Burm, “A 30 MHz Voltage-Mode Buck Converter Using Delay-Line-Based PWM Control,” IEEE Trans. Circ. Syst. II: Exp. Briefs, vol. 65, no. 11, pp. 1659-1663, Nov. 2018.
10. L. Wang, C. Zhan, J. Tang, Y. Liu and G. Li, “A 0.9V 33.7ppm/oC 85nW sub-bandgap voltage reference consisting of subthreshold MOSFETs and single BJT,” IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol. 26, no. 10, pp. 2190-2194, Oct. 2018.